1. Field of the Invention
The present invention relates generally to the field of integrated circuit device configuration. More particularly, the present invention relates to the field of configuration access for integrated circuit devices.
2. Description of Related Art
The Intel(copyright) 450NX PCIset provides an integrated Host-to-Peripheral Component Interconnect (PCI) bridge and memory controller optimized for multiprocessor systems and standard high-volume (SHV) servers. This chipset interfaces with a processor bus that supports up to four Pentium(copyright) II Xeon(trademark) processors and comprises four integrated circuit devices: 82454NX PCI Expander Bridge (PXB), 82451NX Memory and Input/Output (I/O) Bridge Controller (MIOC), 82452NX Row Address Strobe and Column Address Strobe (RAS/CAS) Generator (RCG), and 82453NX Data Path Multiplexor (MUX). The MIOC can support two PXBs to provide two independent PCI buses with an option to link the two buses into a single, wider bus. The MIOC also supports one or two memory cards each comprised of an RCG, a dynamic random access memory (DRAM) array, and two MUXs.
The MIOC accepts access requests from the processor bus and directs those accesses to memory or one of the PCI buses. The MIOC also accepts requests from the PCI buses. The MIOC provides the data port and buffering for data transferred between the processor bus, PXBs, and memory. In addition, the MIOC generates the appropriate controls to the RCGs and MUXs to control data transfer to and from memory. The RCG is responsible for accepting memory requests from the MIOC and converting these into the specific signals and timings required by the DRAM. The MUX provides the multiplexing and staging required to support memory interleaving between the DRAMs and the MIOC.
Each integrated circuit device of the chipset comprises internal control and status registers to configure how the device is to function and to monitor operating conditions of the device. Such registers of each device are accessible through a Joint Test Action Group (JTAG) Test Access Port (TAP) of the device.
A processor coupled to the chipset may also access control and status registers that reside in a configuration space for the MIOC or in either of two configuration spaces for the PXB, one for each PCI bus. Such configuration spaces are accessible through a configuration address register and a configuration data register that reside in the processor I/O address space. The configuration address register identifies a target configuration register or other suitable memory location in accordance with the PCI addressing format for a configuration access request. The configuration data register defines read or write data for a configuration access to the location identified by the configuration address register.
When the MIOC detects an I/O request from a processor is a configuration access request directed to the configuration space of the MIOC, the MIOC performs the configuration access within the MIOC. For configuration reads, the MIOC returns the read data to the processor bus. When the MIOC detects an I/O request from a processor is a configuration access request directed to a PXB configuration space, the MIOC forwards the request to the appropriate PXB. For configuration reads, the PXB performing the read returns the read data to the processor bus through the MIOC.
During system bring-up and debug, however, remote access to the configuration space of the MIOC and PXBs through processor reads and writes may not be possible. Also, any test or debug device using the local JTAG port of the MIOC or PXB must be capable of generating the native configuration protocol for the MIOC or PXB, respectively.
A local integrated circuit device receives configuration access requests through at least two interfaces and accesses a configuration space of one or more remote integrated circuit devices in accordance with the received configuration access requests.